The present invention relates to a semiconductor device of a MIS or MOS structure such as a MOSFET or the like formed on a semiconductor substrate, and more specifically, to this kind of a highly reliable semiconductor device.
Recently, the gate length of a semiconductor device is made very fine with the progress of a fine processing technology for the semiconductor device such as a MOSFET or the like, which permits the degree of integration and the performance of an integrated circuit composed of the MOSFET to be greatly improved. However, as the gate is made fine, various problems arise. These problems include, for example, reduced reliability such as a degradation and the like caused by a hot carrier effect, a reduction in a breakdown voltage between a source and a drain, a short channel effect and the like. They are very disadvantageous in a MOSFET having a gate length of 2 .mu.m or less. The problem of the degradation due to the hot carrier effect arises especially in an n channel MOSFET, and then it will be described below with reference to the n channel MOSFET as an example.
There is, for example, a MOSFET of an LDD (Lightly Doped Drain) structure as a conventional technology which is known best as a means to solve the problem of the degradation of the MOSFET caused by this hot carrier effect, the technology being proposed at the National Convention of the Institute of Electronics and Communication Engineers of Japan, 1978 (paper No. 270 of National Convention Report, Apr. 1978).
FIG. 1 shows a diagram of a structure of a MOSFET of the conventional technology, wherein reference numeral 1 designates a p type substrate, reference numeral 2 designates a gate oxide film, reference numeral 3 designates a gate, reference numeral 4 designates an n type low concentration layer, reference numeral 5 designates a side wall, reference numeral 6 designates a source or drain diffusion layer, reference numeral 7 designates a passivation film, and reference numeral 8 designates source and drain electrodes.
The MOSFET of the LDD structure (referred to as an LDDMOSFET, hereinafter) is characterized in that an offset region of ten n type low concentration layer 4 is provided between the source diffusion layer 6 or the drain diffusion layer 6 and a channel region formed on the lower layer of the gate 3. The LDDMOSFET is manufactured by forming an n type high concentration layer in such a manner that ions are implanted to form the n type low concentration layer 4, using the gate 3 provided on the p type substrate 1 through the gate oxide film 2 as a mask, and then ions are implanted for the source and drain diffusion layers 6 after the side wall 5 has been formed by a silicon oxide film.
With the LDDMOSFET, since the introduction of the n type low concentration layer 4 enables an electric field effect in the channel region in the vicinity of the drain to be eased and a width of a depletion layer extending in the direction of the channel region from the drain to be reduced, the hot carrier effect is prevented, a breakdown voltage between the source and the drain is increased, and the short channel effect is prevented. More specifically, the LDDMOSFET has a less degradation caused by the effect of hot carriers and can establish higher reliability (prevention of malfunction) in a MOSFET with a shorter gate length.
The LDDMOSFET according to the conventional technology, however, has a problem that when it is provided with a shorter gate length, it is subject to a serious degradation caused by hot carriers and cannot maintain reliability. Some models are proposed with respect to a mechanism of the degradation caused by the hot carriers and a degradation mechanism characteristic to the LDDMOSFET will be described with reference to drawings.
FIG. 2A and FIG. 2B are diagrams explanatory of a degradation mechanism of the LDDMOSFET, wherein reference numerals 9, 10, 12 designate electrons, respectively, and reference numeral 11 designates a hole. Like reference numerals used in FIG. 1 describe similar or corresponding parts.
A strong electric field exists at the drain end in the MOSFET, and as shown in FIG. 2A, an electron-hole pair composed of the electron 10 and the hole 11 is created by the electron 9 accelerated there and the electron passes over a potential barrier of the gate oxide film 2, and as shown in FIG. 2B, it advances into the side wall 5 to be caught. The side wall 5 becomes negatively charged by the caught electron 12 and electrons in the n type low concentration layer 4 are reduced in the vicinity of the gate oxide film 2, i.e., in the vicinity of the substrate surface, and thus a resistance of the portion is increased. Then, as described above, the LDDMOSFET according to the conventional technology has the problem that it has a limit in establishing reliability for hot carriers when it is provided with a shorter gate length, and when the gate has a certain length (0.5 .mu.m) or a length less than it, the LDDMOSFET cannot establish the reliability.
As shown in Japanese Patent Publication No. 62-156873, there is a method to connect a spacer (side wall) insulated and separated from a gate electrode to source and drain regions to solve the problem of the hot carriers, but with the method a capacity between a gate and a source or between the gate and a drain is increased and a circuit speed is reduced.
Further, as shown in Japanese Patent Publication 62-122273, there is a method to integrally construct a gate electrode and a conductive side wall structurally or electrically, but this method increases a circuit delay.